Project Description
I need a clear, well-structured set of building and design instructions for the DEC Alpha instruction set, written for someone who is actively designing the processor itself. The focus is on how each arithmetic instruction is implemented at the micro-architectural level and how it interacts with main memory during execution.
Please walk through instruction formats, pipeline stages, control signals, timing, and any associated hazards for the full range of arithmetic operations (add, sub, mul, div, shifts, etc.). Whenever an operation touches main memory—whether for operand fetches, write-backs, or cache-miss recovery—spell out the required signals and timing hand-shakes in the same depth. A concise explanation of where the cache sits in this path is fine, but the write-up should stay centred on the main-memory interface and the internal datapath required to support it.
Deliverables
• A PDF (or Markdown) design manual covering: opcode layout, register map, datapath diagrams, and a worked example for each arithmetic instruction
• Verilog-style pseudocode snippets highlighting the control logic for each stage
• Timing diagrams illustrating memory latency tolerance and stall behaviour
• A short validation checklist I can run against my RTL to confirm correct arithmetic/memory interaction
Acceptance Criteria
All arithmetic instructions must be explained down to cycle-accurate behaviour, with no gaps between the execute stage and main-memory write-back. Diagrams and code should compile or render without edits.
Tools and references such as Alpha Architecture Reference Manual citations, WaveDrom for timing visuals, or Verilog pseudocode are welcome—use whatever communicates the design most effectively.