Project Description
I’m building a small Alpha-ISA processor model and now need the core pieces of the execution engine completed. The focus is on a clean, software-driven control path rather than a hardwired or micro-coded approach, so the design has to expose control signals that a supervisory program can schedule and manipulate.
The hardware side must include:
• ALU that supports the usual arithmetic and logical functions with status outputs ready for branching logic
• Register File with dual-read / single-write ports, parameterisable depth, and a simple hazard-free write-back mechanism
• Instruction Decoder that converts the Alpha binary format into the internal control signal set expected by the software controller
Multiplexer and control unit
I’m happy for you to implement the blocks in Verilog, VHDL, or SystemVerilog—choose whichever fits your workflow—as long as the modules synthesize cleanly in a mainstream FPGA toolchain and come with a self-checking testbench.
Deliverables will be:
1. Source code for each module, clearly commented
2. A top-level wrapper that shows how the software control path interacts with the datapath signals
3. Testbenches (plus scripts) that demonstrate correct operation over a representative instruction mix
4. A brief README explaining how to build, simulate, and extend the design
If you have previous Alpha or RISC pipeline experience, let me know; otherwise, strong RTL skills and clear documentation will win the job.